1. Field Of The Invention
The present invention relates to syntactical rules for software code. More particularly, the present invention adds a high level construct that creates lists and sets of expanded expressions to the syntactical rules for software code, including object-oriented computer languages such as the “C” software language and the N-NARY C hardware design language originally disclosed in the HDL Patent.
2. Description Of The Related Art
N-Nary logic, also known as NDL logic, is a new dynamic logic family developed by Intrinsity Inc. (f/k/a EVSX Inc.), the Assignee of this application. Intrinsity's N-Nary-related technology is trademarked under the name FAST14, and circuits implemented in N-nary logic are denoted as “NDL gates” “NDL circuits” and “NDL designs”, all implemented in “FAST14 technology.” N-Nary logic and the N-Nary design style are described in U.S. Pat. No. 6,066,965, entitled “Method and Apparatus for a N-Nary logic Circuit Using 1-of-4 Signals”, which is incorporated herein for all purposes and is hereinafter referred to as the “NDL Patent.”
Supporting a new logic design style required the invention of new design support techniques and tools to facilitate the computer-aided design and analysis of logic circuits and their constituent subcircuits. Some of these new design support techniques and tools, including a new hardware design language, are disclosed in U.S. Pat. No. 6,289,497, entitled “Method and Apparatus for N-NARY Hardware Description Language” (the “HDL Patent”), and U.S. Pat. No. 6,367,065, entitled “Method and Apparatus for N-NARY Logic Circuit Design Tool with Precharge Circuit Evaluation and U.S. Pat. No. 6,345,381, entitled “Method and Apparatus for a Logic Circuit Design Tool” (the “Design Tools Patents”). The HDL Patent and the Design Tools Patents are owned by Intrinsity, Inc., and all three patents are incorporated by reference for all purposes into this specification.
The HDL Patent and the Design Tools Patents disclose and claim a computer-aided design methodology and tool, and an associated hardware description language similar to “C” that is suitable for use by designers employing the NDL logic design style. As described in the HDL Patent and Design Tools Patents, a designer developing an NDL circuit produces a syntax statement encoded in a combination of ANSI C and the N-nary C language disclosed in the HDL Patent. The syntax statement comprises one or more “gate instantiations,” wherein each gate instantiation contains information regarding the inputs, outputs, and logical function of a gate in the circuit under design. Each gate instantiation includes one or more gate output signal variables, one or more gate operators, and one or more gate expressions. The syntax statement describes both the logical function implemented by the logic circuit being designed and the specific configuration of transistors required to build said circuit. As described in detail in the Design Tools Patents, the design tool compiles the syntax statement and generates both a behavioral model, which is a software-implemented simulation of the logic circuit under design, and a schematic, which is a physical description of the logic circuit under design.
As described in the HDL and Design Tools Patents, each gate expression is explicitly written to enable the design tool to automatically create a circuit having the specifically desired transistor arrangement without much or any further work by a human. The drawback to this approach is that usually, a large number of gate expressions must be written to represent a high-level circuit or logical function. Oftentimes, similar gate expressions are repeated, with only a slight variation of the signal names used in each gate. Writing more equations makes the design more difficult to comprehend and more prone to subtle errors.
The present invention solves this problem by adding constructs governed by specific syntactical rules to the HDL language. The new constructs, collectively designated the “expansion syntax”, are interpreted to expand a single expression into one or more explicit N-Nary C code expressions. The expansion syntax supports specifying high-level constructs in the N-Nary C language, while still maintaining the requirement that each gate be explicitly described in a gate instantiation written in N-Nary C code. Specifying gates using a higher-level construct that is automatically expanded makes the design easier to comprehend and less prone to subtle errors.
While the present invention was developed as a solution to reduce the need for developers to write multiple, nearly-identical gate expressions, and thereby reduce the potential for error, Applicants immediately recognized the applicability of the present invention to any computer language. For example, software designers writing programs in higher-order code must often declare lists of variables, objects, or other named elements, often with only subtle or minor differences in the names of the listed items. Applicants have used the present invention to write gate expressions for NDL circuits as described above, to declare signals and buses in test programs written for simulation, functional verification, or built-in-test programs, in simulation monitors such as that disclosed in U.S. Pat. No. 6,594,803 assigned to Intrinsity, Inc., and in other software programs and applications that require lists of named elements or sets of similar expressions, as indicated by the examples herein.